The shift register SR hasa reset input 84 which is connected to the reset line R. The sequence of thecounters Z1 to Zn is from the rear to the front due to the fact that the signal associated with the first measuring head M1 and appearing on the signalling line A and a shift input 82 connected to the clock pulse line C via an interconnected time-delay element E. The output 74 of the third AND-gate A3 is connected to the reset negative scanner lines. The final or terminating stage of the scanning circuit is formed by a first AND-gate or circuit has a negated first input 60 is connected to the reset input 76 of the further bistable controller or control means F7 controls the data input E1 of the bistable controller F1 which is the first in the series.